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The occupancy of caches has tended to be dominated by the logic bit value '0' approximately 75% of the time. Periodic bit flipping can reduce this to 50%. Combining cache power saving strategies with bit flipping can lower the effective logic bit value '0' occupancy ratios even further. We investigate how Negative Bias Temperature Instability (NBTI) affects(More)
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra-low voltages. Therefore, to operate cells in the subthreshold regime, new cell structures needs to be explored. Towards this, we present a single-ended I/O (SEIO) bit-line latch(More)
This paper proposes a low cost solution to detect and correct a transient faults in registers of a design. The proposed method realizes a single-event upset detection and correction (SEU-DC) technique. The detection and correction of SEU in registers of a design is difficult and requires some efficient approaches without significant area overhead and timing(More)
Steep sub-threshold transistors are promising candidates to replace the traditional MOSFETs for sub-threshold leakage reduction. In this paper, we explore the use of Inter-Band Tunnel Field Effect Transistors (TFETs) in SRAMs at ultra low supply voltages. The uni-directional current conducting TFETs limit the viability of 6T SRAM cells. To overcome this(More)
Low power, minimum transistor count and fast access static random access memory (SRAM) is essential for embedded multimedia and communication applications realized using system on a chip (SoC) technology. Hence, simultaneous or parallel read/write (R/W) access multi-port SRAM bitcells are widely employed in such embedded systems. In this paper, we present a(More)
This paper presents a six-transistor (6T) single-ended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-<i>V</i><sub><i>dd</i></sub> and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell(More)
In this paper, we present a novel six-transistor (6T) single-ended static random access memory (SE-SRAM) cell for ultra-low-voltage applications. The proposed design has a strong 2.65X worst case read static noise margin (SNM) compared to a standard 6T SRAM. A strong write-ability of logic 'one' is achieved, which is problematic in an SE-SRAM cell with a(More)
— In a nanoscale technology, memory bits are highly susceptible to process variation induced read/write failures. To address the above problem, in this paper a new memory cell is proposed which is highly stable against nanoscale process variations as well as power efficient. The effectiveness of the proposed cell is exhaustively evaluated through detailed(More)