Javier A. Salcedo

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Gate oxide breakdown is analyzed under very fast transmission line pulsed (VFTLP) stress, using different pulse-rise times and-widths. The switching of oxide behavior pre-and post-breakdown occurs in tenths of a nanosecond and it shows reproducible voltage and current characteristics. The total stress and time-dependent-dielectric-breakdown (TDDB) during(More)
A new technique is offered as an alternative to extract the threshold voltage of MOSFETs. It defines the threshold at the transition from subthreshold-to-strong inversion operation. Besides its stronger physical foundation, the method provides greater noise and measurement error immunity than conventional methods because, instead of the differentiation(More)
The performance degradation resulting from the addition of ESD protection devices to very high speed Analog/RF designs is the main reason for low ESD robustness in these applications. This paper introduces an ESD methodology that combines device development and characterization as well as simulation, for high speed Analog/RF products. In this work a special(More)
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