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In hierarchical test generation, the test vectors for the low level structure of the module un&r test me computed and then justified at a high level. In the module test computation procedure, a low level ATPG tool is conventionally applied to the complete structure of that particular module without adding extra information. Due to the global circuit(More)
Architectural-level circuit information has been utilized in hierarchical test generation and design for testability in recent years. Analysis at a high level makes a complete gate-level description of the circuit under test unnecessary. In this paper, we propose a new fault simulation technique which uses architectural-level information. This approach(More)