Jaushin Lee

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In hierarchical test generation, the test vectors for the low level structure of the module un&r test me computed and then justified at a high level. In the module test computation procedure , a low level ATPG tool is conventionally applied to the complete structure of that particular module without adding extra information. Due to the global circuit(More)
In this paper, we first present a comparative study of a gate-level test generator and a high-level test generator by benchmarking them on a common suite of circuits. Based on the examination of the results we propose DFT techniques that use high-level circuit information. The results obtained after partial scan selection by a high-level DFT tool are(More)