Jaume Joven

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Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact(More)
—Homogeneous and heterogeneous NoC-based many-core MPSoCs are becoming widespread in many application areas. The diversity and spare network traffic characteristics generated by the IPs makes mandatory to provide certain Quality of Service (QoS) support for critical traffic streams on the system at application level even from the parallel programming model.(More)
— There is some consensus that Embedded and HPC domains have to create synergies to face the challenges to create, maintain and optimize software for the future many-core platforms. In this work we show how some HPC performance analysis methods can be successfully adapted to the embedded domain. We propose to use Virtual Prototypes based on Instruction Set(More)
— The number of resources available in largest reconfigurable devices enables the synthesis of systems with more than 100 Soft-Core processors. Although being a feasible and attainable alternative, few such systems have been built and few works propose methods to create, program and optimize this kind of systems. In this work we present a methodology that(More)
Networks-on-Chip (NoCs) are being increasingly considered as a central enabling technology to communication-centric designs as more and more IP blocks are integrated on the same SoC. Embedded applications, in turn, are becoming extremely sophisticated, and often require guaranteed levels of service and performance. The complex and non-uniform nature of(More)
The aim of this paper is to give briefing of the concept of network-on-chip and programming model topics on multiprocessors system-on-chip world, an attractive and relatively new field for academia. Numerous proposals from academia and industry are selected to highlight the evolution of the implementation approaches both on NoC proposals and on programming(More)
Simulating a NoC at the RTL level can be extremely complex, the simulation of a relatively small NoC, such as a 4x4 mesh, can involve observing thousands of wires on a standard HDL simulator. The facilities of JHDL to extend the simulator environment together with the possibility to fully analyze the runtime object model of the circuit offers a great(More)
Embedded SoC designs are embracing the many-core paradigm to deliver the required performance to run an ever-increasing number of applications in parallel. Networks-on-Chip (NoC) are considered as a convenient technology to implement many-core embedded platforms. The complex and non-uniform nature of the traffic flows generated when multiple parallel(More)