Jatmiko E. Suseno

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Vertical MOSFETs device have one important disadvantage, which is higher overlap capacitances such as the separated gate-source and gate-drain parasitic capacitances (CGSO and CGDO), which is known to be most crucial to the high-frequency/speed performance but very hard to extract. In this paper presents parameter extraction techniques to create an extended(More)
The carrier velocity for 2-dimensional (2-D) p-type nanostructure was simulated in this paper. According to the energy band diagram, the effective mass (m*) in the p-type silicon is mostly dominated by heavy hole because of the large gap between heavy hole and light hole in k = 0. The carrier concentration calculation for 2-D, based on the Fermi –(More)
This paper proposes new method for optimize and verified electric characterization graph of MOSFET by using artificial neural network. Optimization using Neural Network (ONN) will compare current-voltage (I–V) Characteristic graph between the TCAD simulation and TSPICE modeling as desire data control a model parameter of BSIM. In this paper, the(More)
The vertical MOSFET is considered as an alternative to nanoscale device structure, due to relaxed-dependence on lithography and easier double gate realization. In this paper, the influence of body doping concentration variation in vertical MOSFET developed using oblique-rotating implantation (ORI) method is investigated. For this purpose, two-dimensional(More)
The continuous scaling of transistors in nano scale leads to the invention of more sophisticated devices which may possess non-planar structures. As a consequence, the model for respective devices is of importance in order to predict the performance and behaviour throughout its operation. In non-planar structure, the thickness of silicon layer strongly(More)
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