Jatin Bhatia

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Recommended by Huaiyu Dai Design and implementation of a highly optimized MIMO (multiple-input multiple-output) detector requires cooptimization of the algorithm with the underlying hardware architecture. Special attention must be paid to application requirements such as throughput, latency, and resource constraints. In this work, we focus on a highly(More)
This paper reports on a highly optimized 4x4 MMSE detector implementation. The work resulted in a real-time FPGA based implementation on a Xilinx Virtex-II 6000 part. It utilizes 8,513 logic slices, 64 multipliers, and 23 Block RAMs (less than 30% of the overall resources of this part). The design delivers over 420 Mbps sustained throughput, with a small(More)
A real time, 2 Mbps to 200 Mbps portable radio unit with MIMO and sensing capability which exposes all the PHY parameters to the higher layers will help advance experimental cognitive radio (CR), and wireless networking research. Collaboration between Silvus Communication Systems and the UCLA WISR group has resulted in the first generation radio(More)
A real time, 2 Mbps to 150 Mbps portable SDR unit with MIMO and sensing capability which exposes all the PHY parameters to the higher layers will help advance experimental cognitive radio (CR), and wireless networking research. The current SDR implements a slight variant of the 802.11n draft specification, with the entire baseband implemented on a single(More)
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