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Probabilistic arithmetic, where the <i>i<sup>th</sup></i> output bit of addition and multiplication is correct with a probability <i>p<sub>i</sub></i> , is shown to be a vehicle for realizing extremely energy-efficient, embedded computing. Specifically, probabilistic adders and multipliers, realized using elements such as gates that are in turn(More)
We develop a theoretical foundation to characterize a novel methodology for low energy and high performance dsp for embedded computing. Computing elements are operated at a frequency higher than that permitted by a conventionally correct circuit design, enabling a trade-off between <i>error that is deliberately introduced, and the energy consumed</i>.(More)
Highly scaled CMOS devices in the nanoscale regime would inevitably exhibit statistical or probabilistic behavior. Such behavior is caused by process variations, and other perturbations such as noise. Current circuit design method-ologies, which depend on the existence of " deterministic " devices that behave consistently in temporal and spatial contexts do(More)
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