Jaroslav Flidr

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—We introduce a power-aware microsensor architecture supporting a wide operational power range (from <1mW to >10W). The platform consists of a family of modules that follow a common set of design principles. Each module includes a local power microcontroller, power switches, and isolation switches to enable independent power-down control of modules and(More)
Hash functions are among the most widespread cryptographic primi-tives, and are currently used in multiple cryptographic schemes and security protocols such as IPSec and SSL. In this paper, we compare and contrast hardware implementations of the newly proposed draft hash standard SHA-512, and the old standard, SHA-1. In our implementation based on Xilinx(More)
One of the fundamental challenges for modern high-performance network interfaces is the processing capabilities required to process packets at high speeds. Simply transmitting or receiving data at gigabit speeds fully utilizes the CPU on a standard workstation. Any processing that must be done to the data, whether at the application layer or the network(More)
Bandwidth-intensive applications compete directly with the operating system's network stack for CPU cycles. This is particularly true when the stack performs security protocols such as IPsec; the additional load of complex cryptographic transforms overwhelms modern CPUs when data rates exceed 100 Mbps. This paper describes a network-processing accelerator(More)
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