Jaromir Kolouch

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In the paper, a synthesizable combinational integer number divider VHDL model is described that is suitable for implementation in the FPGA devices. The algorithm the divider is based on is briefly introduced. Along the model, testbench for its functional verification is presented. Results of implementation in Xilinx Spartan-3 and Spartan-6 devices —(More)
A proposed system generates a pseudo-chaotic sequence using integer-number look-up-table (LUT). The current output of LUT is used as LUT input address in the next step. The generated sequence approximates or simulates a chaotic sequence. The main facility of the method is high speed of the generating; the main drawback is bounded length of the non-periodic(More)
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