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Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell [1]. A transceiver chip was designed in 0.13µm CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a(More)
To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves(More)
—Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in(More)
– High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit(More)