Jared Zerbe

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—A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10 15 and power equal to 40 mW/Gb/s has been measured when operating over a 20-in(More)
To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only minor modification the same hardware needed to implement a 4PAM system can be used to implement a loop-unrolled single-tap DFE receiver. To get the maximum(More)
Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell [1]. A transceiver chip was designed in 0.13µm CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a(More)
To achieve multi-Gb/s data rates over backplane channels, equalization is required to compensate for the non-idealities of the channels. In this paper, we first show that with decision-feedback equalization (DFE) handling postcursor inter-symbol interference (ISI), cancelling precursor ISI with transmitter equalization degrades rather than improves(More)
—Accurate analysis of system timing and voltage margin including deterministic and random jitter is crucial in high-speed I/O system designs. Traditional SPICE-based simulation techniques can precisely simulate various deterministic jitter sources, such as intersymbol interference (ISI) and crosstalk from passive channels. The inclusion of random jitter in(More)