Learn More
A folded multitap transmitter equalizer and multitap receiver equalizer counteract the losses and reflections present in the backplane environment. A flexible 2-PAM/4-PAM clock data recovery circuit uses select transitions for receive clock recovery. Bit-error rate less than 10 15 and power equal to 40 mW/Gb/s has been measured when operating over a 20-in(More)
To achieve high bit rates link designers are using more sophisticated communication techniques, often turning to 4PAM transmission or decision-feedback equalization (DFE). Interestingly, with only minor modification the same hardware needed to implement a 4PAM system can be used to implement a loop-unrolled single-tap DFE receiver. To get the maximum(More)
A new 1-tap predictive decision feedback equalizer (prDFE), implemented in 40-nm CMOS LP process, achieves 27-Gb/s operation with 0.41-mW/Gb/s power efficiency. The prDFE employs a novel quad-data rate sampling architecture to improve power efficiency while minimizing critical feedback path timing constraint of the equalizer to enable post-cursor(More)
High speed serial data transceivers often employ sophisticated communication techniques to balance out the effects of material loss and reflections. Link control hardware is required to initialize and adapt the link in a variety of signaling environments, often using loops with time constants which are orders of magnitude larger than the data unit interval(More)
To address the increasing demand but potential power/area penalties of implementing ADC-based high-speed serial receivers, this paper analyzes the performance benefit of using non-uniform quantization and describes a way of determining the optimal set of ADC quantization thresholds. In contrast to common wisdom, the ADC thresholds for the minimum bit-error(More)
Common-mode signaling is effectively used to create a backchannel communication path over the existing pair of wires for a self-contained adaptive differential high-speed link transceiver cell [1]. A transceiver chip was designed in 0.13μm CMOS to demonstrate the feasibility of simultaneous differential and common-mode signaling. The design uses a(More)