Janusz Rajski

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This paper presents a novel test-data volume-compression methodology called the embedded deterministic test (EDT), which reduces manufacturing test cost by providing one to two orders of magnitude reduction in scan test data volume and scan test time. The presented scheme is widely applicable and easy to deploy because it is based on the standard scan/ATPG(More)
This paper discusses practical issues involved in applying logic built-in self-test (BIST) to four large industrial designs. These multi-clock designs, ranging in size from 200K to 800K gates, pose significant challenges to logic BIST methodology, flow, and tools. The paper presents the process of generating a BIST-compliant core along with the logic BIST(More)
When the response to a test vector is captured by state elements in scan based tests, the switching activity of the circuit may be large resulting in abnormal power dissipation and supply current demand. High supply current may cause excessive supply voltage droops leading to larger gate delays which may cause good chips to fail tests. This paper presents a(More)
In this paper, we propose a new scheme for BuiltIn Test (BIT) that uses Multiple-polynomial Linear Feedback Shift Registers (MP-LFSR’s). The same MP-LFSR that generates random patterns to cover easy to test faults is loaded with seeds to generate deterministic vectors for difficult to test faults. The seeds are obtained by solving systems of linear(More)
ÐThe paper presents a new fault diagnosis technique for scan-based designs with BIST. It can be used for nonadaptive identification of the scan cells that are driven by erroneous signals. The proposed scheme employs a pseudorandom scan cell selection routine which, in conjunction with a conventional signature analysis and simple reasoning procedure, allows(More)
In this paper we perform a comparative analysis of the encoding efficiency of BIST schemes based on reseeding of single polynomial LFSR's as well as LFSR's with fully programmable polynomials. Full programmability gives much better encoding efficiency. For a testcube with s carebits we need only s+4 bits in contrast to s+19 bits for reseeding of single(More)
This paper presents the impact of multiple-detect test patterns on outgoing product quality. It introduces an ATPG tool that generates multiple-detect test patterns while maximizing the coverage of node-tonode bridging defects. Volume data obtained by testing a production ASIC with these new multipledetect patterns shows increased defect screening(More)