Jani Paakkulainen

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Tapani Ahonen*, Seppo Virtanen**, Juha Kylliäinen*, Dragos Truscan***, Tuukka Kasanko*, David Sigüenza-Tortosa*, Tapio Ristimäki*, Jani Paakkulainen**, Tero Nurmi**, Ilkka Saastamoinen*, Hannu Isännäinen*, Johan Lilius***, Jari Nurmi*, and Jouni Isoaho** *Institute of Digital and Computer Systems, Tampere University of Technology, Finland **Department of(More)
Programming multicore systems is currently considered very difficult. One reason is that those are mostly constructed from the hardware point of view. Many of the processor core design solutions in contemporary constructions emphasize execution speed of a single thread. Since the memory access delay is the real bottleneck, such techniques often aim at(More)
To meet the tightening requirements on network hardware, the design of programmable processors with network-optimised hardware, that is, network or protocol processors, has attracted interest. In this paper, we address evaluation of different architectural configurations for such processors, and reuse of previously designed components in later design(More)
We present a case study in finding optimized processor architectures for a given protocol processing application. The process involves application analysis, hardware/software partitioning and optimization, and evaluation of design quality through simulations, estimations and synthesis. The case study was targeted at processing key IPv6 routing functions at(More)
Designing a parallel computer architecture for the multi-core on chip environment involves a lot of architectural design issues. Actual hardware design based on ASIC and for demonstrational purposes on FPGA is very expensive method to study the cost of various design choices. Therefore, we have developed a software based simulator MVTsim for multi-core on(More)
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