Janet M. Wang

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Today's main stream NVM technologies require operational conditions that are incompatible with modern low voltage logic CMOS designs. This characteristic results in complex integration issues as well as costly process and array concept especially for embedded NVM use models. Conductive bridging memory cell (CBRAM) technology is an attractive emerging memory(More)
New nanotechnology based devices are replacing CMOS devices to overcome CMOS technology’s scaling limitations. However, many such devices exhibit nonmonotonic I-V characteristics and uncertain properties which lead to the negative differential resistance (NDR) problem and the chaotic performance. This paper proposes a new circuit simulation approach that(More)
Network-on-Chip (NoC) architectures provide a scalable solution to the wire delay constraints in deep submicron Very Large Scale Integrated circuit (VLSI) designs. To reduce power consumption and improve performance, we propose in this paper a technique which provides high speed link design by utilizing a compact model for repeater insertion that takes into(More)
This paper presents thorough survey of work addressing on load balancing in recent computing trends. There are many issues whose solutions lead to the need for load balancing. The objective of load balancing is to increase the performance of parallel and distributed system by distributing the load among the processors. Load balancing is a major factor for(More)
In nanoscale technologies process variability makes it extremely difficult to predict the behavior of manufactured integrated circuits (IC). The problem is especially exacerbated in analog IC where long design cycles, multiple manufacturing iterations, and low performance yields causes only few design to have the volume required to be economically viable.(More)
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