Jan Vytopil

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This paper indicates a method of describing real-time processes and their asynchronous communication by means of message exchanges. This description method is based upon an extension of linear time temporal logic to a special temporal logic in which real-time and asynchronous message passing properties can be expressed. We give a model of this logic, define(More)
In this paper, we present a performance prediction model for indicating the performance range of MIMD parallel processor systems for neural network simulations. The model expresses the total execution time of a simulation as a function of the execution times of a small number of kernel functions, which have to be measured on only one processor and one(More)
PREENS { a Parallel Research Execution Environment for Neural Systems { is a distributed neurosimulator, targeted on networks of workstations and transputer systems. As current applications of neural networks often contain large amounts of data and as the neural networks involved in tasks such as vision are very large, high requirements on memory and(More)
This report describes convis, an action oriented neurosimulator providing control over a neural network simulation program and visualization of the data associated with it. It is a manager that controls a simulation program, and manages any tools that input or output data into or from the program. A technical description of the features that are supported(More)
A performance prediction method is presented for indicating the performance range of MIMD parallel processor systems for neural network simulations. The total execution time of a parallel application is modeled as the sum of its calculation and communication times. The method is scalable because based on the times measured on one processor and one(More)
This report presents new results from work performed in the framework of the IC 3 A programme. Using the GCel-512 and the PowerXPlorer made available by the UvA, a performance prediction model for several neural network simulations could be validated quantitatively both for a larger processor grid and for a diierent target parallel processor conngu-ration.(More)
  • W P De, Roever-H Barringer-C, D Courcoubetis, R Gabbay, Gerth-B, onsson-A +16 others
  • 2001
Since many of these notes are preliminary versions or may be published elsewhere, they have a limited distribution only and are not for review. Copies of these notes are available from the author or the editor. of the sections on objectives and area of advance, on baseline and rationale, on research goals, and on organisation of the action, as contained in(More)
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