Jan Vandewege

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In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node. The processor has an architecture optimized to handle flow processing tasks such as parsing, classification and packet manipulation. The VLIW instruction set allows for high degree of parallelism among the(More)
A novel large input range source-follower based bi-quad filter cell is proposed offering an additional degree of freedom to the position of the poles and zeros. Simulation results of a 4th order fully differential elliptical filter in a 0.13 μm CMOS technology confirm a power consumption of 160 μA @ 1.2 V, an IIP3 of 6.3 dBm and a steep-ness of 177(More)