In this paper we present an embedded implementation of a Traffic Light Recognition (TLR) on a low-cost FPGA device with low memory usage.We follow a systematic approach where we thoroughly investigate computational hot-spots, and systematically partition the system into hardware and software components which we both optimize. Our implementation is evaluated… (More)
Video applications are moving from Full-HD capability (1920x1080) to even higher resolutions such as Quad-FullHD (3840x2160). The H.264 Intra-mode can be used by embedded devices to trade off the better encoding efficiency of H.264 temporal prediction (Inter-mode) against savings in area and power as well as saving the massive computational overhead of the… (More)
This paper presents a demonstrator for a largely task-parallel implementation of an automotive Advanced-Driver-Assistance-System (ADAS). Targeting the Intel SCC<sup>1</sup>  48-core chip, we show the scalability of this application towards a configurable number of cores up to 25.
In this paper, we present a novel runtime resource management approach that obeys automotive safety constraints. We specifically target emerging heterogeneous embedded plat-forms which promise potential to ease the ever-growing gap between demanded processing power and feasible efficient em-bedded realization of modern assistance systems by allowing both,… (More)
We present a fast and accurate timing simulation of binary code execution on complex embedded processors. Underlying block timings are extracted from a preceding hardware execution and differentiated by execution context. Thereby, complex factors, such as caches, can be reflected accurately without explicit modeling. Based on timings observed in one… (More)