Jan Fandrianto

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An algorithm to implement radix four division and radix four square-root in a shared hardware for IEEE standard for binary floating point format will be described. The algorithm is best suited to be implemented in either off-the-shelf components or being a portion of a VLSI floating-point chip. Division and square-root bits are generated by a non-restoring(More)
The advance of VLSI technology has been the enabling factor in the appearance of VLSI circuits handling floating-point arithmetics. These circuits have found their way into many number-crunching applications such as telecommunications, seismic energy exploration, radar, medical imaging, graphics and simulation. Because of the different requirements for(More)
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