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Physical design for analog ICs has not been automated to the same degree as digital IC design, but such automation can significantly improve the productivity of circuit engineers. Analog design remains difficult to formalize due to a large amount of expert knowledge involved, such as sophisticated constraints that are specified manually and satisfied(More)
The increasing quality requirements on safety-critical electronic components and the rapid technological progress necessitate the compliance with all specified functional and non-functional design constraints. This paper introduces a novel verification method based on an unified data representation of constraints to enable multi-tool verification tasks. A(More)
Evaluation and refinement of system models often require modifications in the model that follow concrete rules. In this work, a method for a flexible automation of such transformation steps will be presented. It allows savings in development time and reduces the error proneness. Therefore, a tool for rule based manipulation of VHDL design descriptions has(More)
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