James P. Cohoon

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This paper presents a new model for VLSI routing in the presence of obstacles, that transforms any routing instance from a geometric problem into a graph problem. It is the first model that allows computation of optimal obstacle-avoiding rectilinear Steiner trees in time corresponding to the instance size (the number of terminals and obstacle border(More)
A placement algorithm, Genie, is presented for the assignment of modules to locations on chips. Genie is an adaptation of the genetic algorithm technique that has traditionally been a tool of the artificial intelligence community. The technique is a paradigm for examining a state space. It produces its solutions through the simultaneous consideration and(More)
Floorplan design is an important stage in the VLSI design cycle. Designing a floorplan calls for arranging a given set of modules in the plane to minimize the weighted sum of area and wirelength measures. This paper presents a method to solve the floorplan design problem using distributed genetic algorithms. Distributed genetic algorithms, based on the(More)
The island model genetic algorithm shows promise as a superior formulation based on considerations from theories of natural evolution and from the efficiencies of coarsegrained parallel computer architectures. The theory of punctuated equilibria calls for the population to be partitioned into several distinct subpopulations. These subpopulations have(More)
This paper presents an algorithm that computes an optimal rectilinear Steiner minimal tree of n points in at most O(n 2 2:62 n) time. For instances small enough to solve in practice, this time bound is provably faster than any previous algorithm, and improves the previous best bound for practically solvable instances, which is O(n3 n). Experimental evidence(More)
We explore physical layout for a three-dimensional (3D) FPGA architecture. For placement, we introduce a top-down partitioning technique based on rectilinear Steiner trees; we then employ a one-step router to produce the nal layout. Experimental results indicate that our approach produces eeective 3D layouts, using considerably shorter average interconnect(More)