James A. Slinkman

Learn More
This paper describes a 180nm CMOS thin film SOI technology developed for RF switch applications. For the first time we show that the well-known harmonic generation issue in HRES SOI technologies can be suppressed with one additional mask. Power handling, linearity, and Ron*Coff product are competitive with GaAs pHEMT and silicon-on-sapphire technologies.(More)
Over the past few years, CMOS Silicon-oninsulator (SOI) has emerged as the dominant technology for RF switches in RF front end modules for cell phones and WiFi. RF SOI technologies were created from silicon processes originally used for high speed logic applications, but the technology was modified to meet the performance needs of RF switches. The RF SOI(More)
Many of the processes used in the fabrication of siiicon Integrated circuits iead to the development of stress In the silicon substrate. Given enough stress, the substrate will yield by generating dislocations. We examine the formation of stress-induced dislocations in integrated circuit structures. Examples are presented from bipolar and lUIOS-based(More)
This paper describes a single pole, single throw (SPST) 180nm CMOS thin film SOI switch developed for the most difficult cellular and 802.11x RF switch applications. We will show that power handling, linearity, insertion loss, isolation and switching times are competitive with switch applications utilizing GaAs pHEMT and siliconon-sapphire technologies.(More)
We have applied a simultaneous combination of scanning Kelvin probe microscopy and scanning atomic force microscopy to the problem of pro ling dopant concentrations in two dimensions in silicon microstructures. By measuring the electrochemical potential di erence which minimizes the electrostatic force between probe tip and sample surface, we estimate the(More)
In this study, we define and investigate the maximum power handling capability (Pmax) in an SOI RF shunt branch switch. One of the critical factor in the Pmax is the non-uniform voltage division across an OFF shunt branch. In this study we provide a simple analytical method to determine the stack voltage imbalance. The Pmax is characterized as a function of(More)
A novel numerical approach to solving Schr odinger's equation as applied to quantum well heterostructures is described. The quantum mechanical energy subbands, wave functions and charge density are calculated based on a two-directional fourthorder Runge-Kutta (RK4) algorithm. The algorithm is applied to well-de ned quantum well structures. Results are(More)
A fabrication induced failure in complementary metal-oxide-semiconductor dynamic random access memory (CMOS DRAM) cells has been imaged successfully with a novel combination of atomic force and scanning Kelvin probe microscopes. The imaging system was used to verify the presence, and subsequent removal of, ionic contaminants on a sub-micron scale.
Incorporation of a Si1 xGex alloy layer in the channel of a p-channel MOSFET has been proposed as a means to improve device performance [1, 2]. In order to achieve optimal performance in such a device, the inversion charge distribution must be located in the alloy channel layer where the carrier mobility is highest [3]-[6]. The smaller bandgap of the Si1(More)
The Ridley Third Body Exclusion scattering formula for ionized impurities has been examined in a Monte Carlo simulation of low eld bulk mobility for compensated n-type silicon. When the material is lightly doped (Nd 10 cm ) and for lattice temperatures higher than 100 K the scattering formula results in an estimate for the bulk mobility that is comparable(More)
  • 1