Jakub Janicki

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Growing test data volume and excessive test power consumption in at-speed scan testing are both serious concerns for the semiconductor industry. This paper presents a method to simultaneously reduce test data volume and test power in atspeed delay test utilizing clock gating. This is achieved through not clocking a high proportion of scan chains during both(More)
This paper presents preemptive test application schemes for system-on-a-chip (SoC) designs with embedded deterministic test-based compression. The schemes seamlessly combine new test data reduction techniques with test scheduling algorithms and novel test access mechanisms devised for both input and output sides. In particular, they allow cores to interface(More)
This paper presents novel methods of reducing test time and enhancing test compression for system-on-chip (SoC) designs armed with embedded deterministic test (EDT)-based compression logic. The ability of the proposed scheme to improve the encoding efficiency and test compression, while reducing test application time, is accomplished by appropriate(More)
This paper presents novel methods of enhancing test compression solutions for SoC designs. The ability of the proposed schemes to improve the encoding efficiency, test compression, and test time is accomplished by either appropriate selecting or laying out ATE channel injectors within EDT-based decompressors. The efficacy of new techniques with respect to(More)
in the Mentor Graphics Polska. Numerous people helped me through this effort and I would like to mention some of them here. I would like to express my sincere gratitude to my supervisor Professor Jerzy Tyszer. His guidance, enthusiasm, inspiration, insightful remarks, and, last but not least, continual motivation were all invaluable. I will never forget the(More)