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Scan Compression design solutions integrated into an SoC offers tradeoffs between reduction of test time and test data volume based on the allocation of tester channels amongst various IPs. This paper presents a heuristic to provide significant test time improvement yet reducing the overall test data volume.
complexity of the functionalities and the resultant growth in number of gates integrated in a chip coupled with shrinking geometries and short cycle time requirements bring in several challenges into the design of present day VLSI chips. In this paper we present the challenges faced and the approaches successfully adopted in the design of a complex 2.5… (More)
Innovative solutions have been proposed to reduce the test cost of SOC designs. STUMPS (self-test using PRPG and MISR structures) architecture based logic BIST (built-in self-test) is one such popular solution which attempts to reduce the cost of scan based tests by exploiting shorter scan chains in the design. To address the lower test coverage attainable… (More)