Jagdeep Kaur Sahani

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This paper presents a design of a one bit full adder cell based on degenerate pass transistor logic (PTL) using Double Gate MOSFET. The design cell is degenerate 5-T XOR-XNOR module. This design has been compared with existing one-bit full adder cell based on degenerate pass transistor logic (PTL) designed using Single Gate MOSFET. In this paper, the(More)
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