Jagannathan Narasimhan

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In this paper, we describe a simple and rapid method of fabricating hot embossing tools using polydimethylsiloxane (PDMS), which are then used to rapidly fabricate microchannels in polymethylmethacrylate (PMMA). A negative photoepoxy SU-8 or thick positive photoresist AZ4620 on silicon was used for molding during PDMS casting. Fabrication time of these PDMS(More)
In this paper, we address the problem of generating good topologies of rectilinear Steiner trees using path search algorithms. Various techniques have been applied in order to achieve acceptable run times on a Maze Router that builds Steiner trees. A biasing technique proposed for wire length improvement, produces trees that are within 2% from optimal(More)
In this paper, we describe methods to speed up integrated placement and synthesis of high performance designs. We present an analysis of the computation times of various logic synthesis transforms. We then show techniques to reduce computation time based upon judicious selection of gates and nets for the resizing and buffering transforms, respectively. We(More)
The fault diagnosability problem is the problem of computing the maximum number of faulty units which a system can tolerate without losing its capability of identifying all such faulty units. We study this problem for the model introduced by Barsi, Grandoni, and Maestrini [2]. We present a new characterization of the model, and develop an efficient(More)
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