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This paper presents a zero-skew gated clock routing technique for VLSI circuits. Gated clock trees include masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce the switched capacitance of the clock tree. We construct a… (More)

This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the routing area is kept to a minimum. We first show that proper p/g terminal to pad assignment is necessary to… (More)

This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. This work extends the… (More)

This paper presents an exact algorithm and two heuristics for solving the Bounded path length Minimal Spanning Tree (BMST) problem. The exact algorithm which is based on iterative negative-sum-exchange(s) has polynomial space complexity and is hence more practical than the method presented by Gabow. The first heuristic method (BKRUS) is based on the… (More)

Software-as-a-Service is becoming popular in the software business, due to its rapid delivery and cost effectiveness in development and maintenance. Software-as-a-Service should be provided in single code base and operated as a single instance. To meet these constraints and requirements from various customers, Software-as-a-Service must be highly… (More)

This paper presents a zero-skew gated clock routing technique for VLSI circuits. The gated clock tree has masking gates at the internal nodes of the clock tree, which are selectively turned on and off by the gate control signals during the active and idle times of the circuit modules to reduce switched capacitance of the clock tree. The clock tree topology… (More)

This paper presents a new approach for solving the Lower and Upper Bounded delay routing Tree (LUBT) problem using linear programming. LUBT is a Steiner tree r o oted at the source node such that delays from the source to sink nodes lie between the given lower and upper bounds. We show that our proposed method p r o duces minimum cost LUBT for a given… (More)

We develop a new method to map (i.e. allocate and schedule) real-time applications into certain multiprocessor systems. Its objectives are 1) the minimization of the number of processors used and 2) the minimization of the deadline missing time. Given a parallel program with real time constraints and a multiprocessor system, our method finds schedules of… (More)