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Today's IEEE 802.11 Wireless LAN (WLAN) is an excellent solution for the broadband wireless networking. However, it lacks of the capability to support real-time services such as Voice-over-IP (VoIP) properly. In this paper, we present a simple and viable approach to enhance the VoIP performance over the 802.11 WLAN by implementing two queues along with a(More)
—Smart Grid applications are imposing challenging requirements of security and reliability on the N-way communication infrastructure being designed to support multiple grid applications. These challenges stem from the increasing incorporation of distributed renewable energy sources on to the grid, the rising deployment of electric vehicles, and active(More)
This paper proposes a novel Deadlock Avoidance Algorithm (DAA) and its hardware implementation, the Deadlock Avoidance Unit (DAU), as an Intellectual Property (IP) core that provides a mechanism for very fast and automatic deadlock avoidance in MultiProcessor System-on-a-Chip (MPSoC) with multiple (e.g., 10) processing elements and multiple (e.g., 40)(More)
In this paper, we show the performance comparison and analysis result among three RTOSes: the Real-Time Unit (RTU) hardware RTOS, the pure software Atalanta RTOS and a hardware/software RTOS composed of part of Atalanta interfaced to the System-on-a-Chip Lock Cache (SoCLC) hardware. We also present our RTOS configuration framework that can automatically(More)
Intertask/interprocess synchronization overheads may be significant in a multiprocessor-shared memory System-on-a-Chip implementation. These overheads are observed in terms of lock latency, lock delay and memory bandwidth consumption in the system. It has been shown that a hardware solution brings a much better performance improvement than the(More)
The majority of CPUs now sold contain multiple computing cores. However, current desktop grid computing systems either ignore the multiplicity of cores, or treat them as distinct, independent machines. The former approach ignores the resource contention present between cores in a single CPU, while the latter approach fails to take advantage of significant(More)