Jae-Whui Kim

Publications45
h-index13
Citations557
Highly Influential Citations28
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A new level-up shifter for high speed and wide range interface in ultra deep sub-micron
TLDR
A new level-up shifter aimed at ultra low core voltage and wide range I/O voltage is designed using a 90 nm CMOS process. Expand
  • 82
  • 5
  • PDF
An All-Digital 90-Degree Phase-Shift DLL with Loop-Embedded DCC for 1.6Gbps DDR Interface
TLDR
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 4pi radians. Expand
  • 25
  • 5
A fully-differential zero-crossing-based 1.2V 10b 26MS/s pipelined ADC in 65nm CMOS
TLDR
A fully-differential zero-crossing-based 10b 26 MS/s pipelined ADC in a 65 nm CMOS process that achieves 54.3 dB SNDR with 161 fJ/step. Expand
  • 67
  • 4
  • PDF
A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC
  • M. Kim, G. Ahn, +6 authors U. Moon
  • Engineering, Computer Science
  • IEEE Journal of Solid-State Circuits
  • 22 April 2008
TLDR
A new method using a combination of a switched-RC technique and a floating switched-capacitor double-sampling configuration enabled low-voltage operation without clock boosting or bootstrapping. Expand
  • 63
  • 2
  • PDF
A 1 mW 10-bit 500KSPS SAR A/D converter
TLDR
A 1mW 1.5 V 10-bit 500 KSPS successive approximation (SAR) analog-to-digital converter (ADC) was fabricated in a 0.25 um CMOS technology. Expand
  • 29
  • 2
A 2W, 92% efficiency and 0.01% THD+N class-D audio power amplifier for mobile applications, based on the novel SCOM architecture
TLDR
This paper presents a high power efficient class-D audio power amplifier adopts the synchronized controlled oscillation modulator (SCOM), which is suitable for mobile applications. Expand
  • 22
  • 2
A 1.5 V 10-bit 25 MSPS pipelined A/D converter
A 1.5 V 10-bit 25 MSPS pipelined analog-to-digital converter was implemented using 0.25 /spl mu/m CMOS technology. The converter is based on low-voltage two-stage opamps and a current reference… Expand
  • 4
  • 2
A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control
  • M. Choi, Sung-No Lee, +4 authors H. Lee
  • Physics, Computer Science
  • IEEE Custom Integrated Circuits Conference
  • 17 November 2008
TLDR
A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. Expand
  • 26
  • 1
A 0.9V 92dB Double-Sampled Switched-RC SD Audio ADC
  • M. Kim, G. Ahn, +6 authors U. Moon
  • Computer Science
  • Symposium on VLSI Circuits, . Digest of Technical…
  • 15 June 2006
TLDR
A 0.9V third-order 1.5bit delta-sigma ADC with simple dynamic element matching (DEM) is presented with 92dB DR, 91dB SNR and 89dB SNDR. Expand
  • 13
  • 1
  • PDF
Slew-Rate-Controlled Output Driver Having Constant Transition Time Over Process, Voltage, Temperature, and Output Load Variations
TLDR
A slew-rate-controlled output driver having a constant transition time irrespective of environmental variations is described in this brief. Expand
  • 13
  • 1