Jae-Joon Kim

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Ultra-low voltage operation of memory cells has become a topic of much interest due to its applications in very low energy computing and communications. However, due to parameter variations in scaled technologies, stable operation of SRAMs is critical for the success of low-voltage SRAMs. It has been shown that conventional 6T SRAMs fail to achieve reliable(More)
This paper presents a forward body-biasing (FBB) technique for active and standby leakage power reduction in cache memories. Unlike previous low-leakage SRAM approaches, we include device level optimization into the design. We utilize super high Vt (threshold voltage) devices to suppress the cache leakage power, while dynamically FBB only the selected SRAM(More)
AIM To verify that CD markers are available for detecting cancer stem cell populations and to evaluate their clinical significance in colon cancer. METHODS Immunohistochemistry for CD133, CD24 and CD44 was performed on the tissue microarray of 523 colorectal adenocarcinomas. Medical records were reviewed and clinicopathological analysis was performed. (More)
Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)) weaken MOSFETs with time. The impact of such device degradation can be severe in Static Random Access Memories (SRAMs) wherein stability is governed by relative strengths of FETs. Degradation in stability with time under ‘worst case condition’ gets more important(More)
This paper presents a completely on-chip digital circuit to measure local threshold-voltage variation using an array of identical devices under test (DUTs) stacked with a single reference device. This technique detects on-chip variation of single devices, rather than matched device pairs or SRAM cells. The variation in V<sub>t</sub> of the DUTs is detected(More)
The stability and performance characteristics of Static Random Access Memories (SRAMs) are known to degrade with time due to the impact of Negative and Positive Bias Temperature Instabilities (NBTI (in PFET) and PBTI (in NFET)). In this work, we provide insights into relative sensitivities of these phenomena on speed and stability of SRAM cells. Relative(More)
Increasing variations in device parameters significantly degrades the write-ability of SRAM cells in deep sub-100 nm CMOS technology. In this paper, a transient negative bit-line voltage technique is presented to improve write-ability of SRAM cell. Capacitive coupling is used to generate a transient negative voltage at the low-going bit-line during Write(More)
This paper reviews the design challenges and techniques of high-performance SRAM in the "End of Scaling" nanoscale CMOS technologies. The impacts of technology scaling, such as signal loss due to leakage, degradation of noise margin due to V<sub>T</sub> scatter caused by process variations and random dopant fluctuation, and long term reliability degradation(More)
This paper presents a forward body-biasing (FBB) scheme for active leakage power reduction in cache memories. We utilize super high VT (threshold voltage) devices to suppress the leakage power in unselected portions of a cache while fast operation is achieve by dynamically forward body-biasing the selected SRAM cells. In order to generate a super high VT(More)
The pronounced impact of process uncertainties on the power-performance characteristics of systems has necessitated characterization and design efforts that aim to maximize the parametric yield of the design. This paper describes a completely digital on-chip technique to measure local random variation of FET current. The measurement circuit consists of a(More)