Jacobus W. Swart

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A novel multisampling time-domain architecture for CMOS imagers with synchronous readout and wide dynamic range is proposed. The architecture was implemented in a prototype of imager with 32x32 pixel array fabricated in AMS CMOS 0.35µm and was characterized for sensitivity and color response. The pixel is composed of an n+/psub photodiode, a comparator(More)
This paper presents a radiation hardened Active Pixel Sensor implemented in a standard 0.35μm CMOS process. The integrated circuit is composed of a 64x64 pixel matrix with a 25μm pixel pitch and has four different pixel architectures. There are also test structures to permit the characterization of the MOS transistors. The radiation hardening of(More)
A set of low noise transimpedance amplifiers fabricated and characterized in CMOS and BiCMOS technologies are proposed in this work. Layout optimization, efficient modeling and bias point optimization are the techniques employed to reduce the input noise current density. The CMOS amplifiers were designed to work at 10 Gbps. The BiCMOS amplifiers, based on(More)
Design guide lines are given for developing SiGe HBT mm-wave d.c. coupled ultra-wide-band low noise monolithic amplifiers. An ultra wide band LNA and two mm-wave TIAs for 40 Gbps and 100 Gbps applications are proposed. The LNA has S21=11 dB and a 3-dB bandwidth of 88 GHz. The 40 Gbps TIA has a new topology, allowing a DC coupled performance, 54 dBΩ(More)
Image sensors in standard CMOS technology are increasing used for consumer, industrial and scientific applications due to their low cost, high level of integration and low power consumption. Further, image sensors in mainstream complementary metal-oxide-semiconductor (CMOS) technology are preferred because they are the lowest cost and easiest/fastest option(More)
The regulated cascode (RGC) is a widely used topology in transimpedance amplifiers projects. Although it is efficient with respect to power consumption and bandwidth, the regulated cascode presents high input-referred current noise levels that hinder the use of this topology in long distance optical networks. In this paper is proposed a design methodology(More)