In this paper we present a simplified model of parallel, on-chip buses, motivated by the movement toward CMOS technologies where the ratio between inter-wire capaci-tance and wire-to-ground capacitance is very large. We also introduce a ternary bus state representation, suitable for the bus model. Using this representation we propose a coding scheme without… (More)
there are lower bounds for the maximal number of codewords in binary frame-proof codes and decoders in traceability schemes. There are also existence proofs using a construction of binary frame-proof codes and traceability schemes. Here it is found that the main results in the referenced paper do not hold.
A coding technique for deep sub-micron address buses with inter-wire capacitances dominating the wire-to-ground capacitances is presented. This code is similar to Gray codes, in the sense that it defines an ordering of the binary space, such that adjacent codewords dissipate little energy when sent consecutively. The ordering is shown to be close to… (More)