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Journals and Conferences
This paper presents a methodology to use global and local performance sensors, allowing the circuits to be optimized for power and/or performance.
This paper presents a new aging sensor architecture for error prediction of performance errors in synchronous digital circuits. The aging sensor is based on a new flip-flop with built-in logic that… (More)
This paper presents an analysis of the implications of clock gating techniques on the increase of aging degradations in new node digital circuits. NBTI is the dominant effect that cause long-term… (More)