Jack Kenney

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A continuous-rate CDR based upon a digital dual delay/phase locked loop is reported. This CDR is implemented in 0.13&#x03BC;m CMOS and operates from 6.5Mb/s to 11.3Gb/s. It exceeds all SONET jitter specifications from OC-3 to OC-192, with random jitter of 452fs at 9.95Gb/s. The die area is 2&#x00D7;2mm<sup>2</sup>, and is implemented in a 24-pin LFCSP.
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