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A 28.5-32-GHz fast settling multichannel frequency synthesizer is implemented in 0.25-mum SiGe : C BiCMOS process technology for 60-GHz wireless personal area network (WPAN) applications. The phase-locked loop (PLL) synthesizes carrier frequencies between 28.5-32 GHz in step of 500 MHz, and settles in approximately 327 ns. The proposed PLL can be employed(More)
A 45 - 60-GHz two-band double cross-coupled differential VCO is designed and fabricated using 0.25 mum SiG:C BiCMOS process technology whose f<sub>max</sub> is greater than 200 GHz. The VCO provides tuning ranges of 44.9 - 48.9 GHz when its bias current is 13 mA and of 58 - 60.4 GHz when a bias current of 7 mA draws into the VCO. The phase noises of the VCO(More)
In this paper, we present the design of 15-GHz frequency synthesizer for 60-GHz WPAN. The PLL generates 7 channels of output signals with 250 MHz step by using the highspeed programmable divider operating up to 10 GHz. A double cross-coupled LC VCO is used for achieving higher oscillation frequency and shows about 20 % tuning range. The PLL represents phase(More)
In this paper, we present a 3.8-5.5 GHz multi-band CMOS frequency synthesizer for WLAN and UWB applications. In the multi-band frequency synthesizer, both new multi-mode prescaler and adaptive multi-band LC VCO are proposed. The proposed multi-mode prescaler produces six modes of divide-by-2/3, 4/5, 8/9, 16/17, 32/33, and 64/65. In the adaptive multi-band(More)
In this paper, a 9.1 to 11.5 GHz four-band PLL is presented. In the proposed PLL, both an improved multi-modulus (MM) divider and an adaptive four-band LC VCO are depicted. The MM divider provides division ratios of 6 to 455 depending on the division mode of the six-mode prescaler. The LC VCO generates four bands of oscillation frequencies covering 9.1-11.6(More)
This paper presents an all-digital fractional-N PLL with a low-power TDC operating at the retimed reference clock. Two retimed reference clocks are employed to implement the proposed TDC estimating the fractional phase error between the reference clock and CKV clock. The application of the retimed reference clocks to TDC does not only reduce dynamic power(More)
In this paper, we present the design of 52-GHz frequency synthesizer for 60 GHz WPAN application. The PLL consists of 26 GHz PLL and 52 GHz frequency doubler, generating two channels of output carriers with 2.08 GHz step by using high-speed four-modulus divider. The proposed PLL represents phase noise of - 89 dBc/Hz from 26.2 GHz carrier and - 81 dBc/Hz(More)
In this paper, a 60 GHz MMIC down-conversion mixer for 60 GHz WPAN is designed and fabricated on chip using 0.25 mum SiGe:C BiCMOS process technology. This 60 GHz mixer is fully integrated on chip, including active input balun and output balun circuits. The results of the fabricated mixer measured at RF 60 GHz show conversion gain of 10.7 dB, LO to IF(More)