• Publications
  • Influence
A 65nm logic technology featuring 35nm gate lengths, enhanced channel strain, 8 Cu interconnect layers, low-k ILD and 0.57 /spl mu/m/sup 2/ SRAM cell
  • P. Bai, C. Auth, +32 authors M. Bohr
  • Materials Science
  • IEDM Technical Digest. IEEE International…
  • 1 December 2004
A 65nm generation logic technology with 1.2nm physical gate oxide, 35nm gate length, enhanced channel strain, NiSi, 8 layers of Cu interconnect, and low-k ILD for dense high performance logic isExpand
  • 271
  • 17
  • PDF
High performance 32nm logic technology featuring 2nd generation high-k + metal gate transistors
A 32nm logic technology for high performance microprocessors is described. 2nd generation high-k + metal gate transistors provide record drive currents at the tightest gate pitch reported for anyExpand
  • 198
  • 15
  • PDF
A 65nm ultra low power logic platform technology using uni-axial strained silicon transistors
  • C. Jan, P. Bai, +29 authors B. Holt
  • Engineering
  • IEEE InternationalElectron Devices Meeting…
  • 5 December 2005
A leading edge 65nm logic process technology employing uni-axial strained silicon transistors has been optimized for ultra low power products. Record PMOS/NMOS drive currents of 0.38/0.66 mA/mum,Expand
  • 55
  • 6
Théorie des réseaux de Kirchhoff
  • 11
  • 2
Realisability of bandpass filters
The traditional method of realising attenuation poles by resonant circuits is questioned. Expand
  • 3
  • 1
Nonlinear Circuits
  • 129
Dynamics of a piecewise-linear resonant circuit
The qualitative nature of the time evolution in a piecewiselinear lossy resonant circuit driven by sinusoidal voltage source is investigated by computer-aided analysis using exact analytical formulas. Expand
  • 62
Equal ripple tolerance characteristics
The concept of equal ripple tolerance is introduced and justified in the particular case of the polynomial low pass filter. By comparison with the classical Chebyshev characteristic, it is shown thatExpand
  • 16
Scaling challenges for 0.13 /spl mu/m generation shallow trench isolation
Scaling shallow trench isolation (STI) from the 0.18 /spl mu/m to 0.13 /spl mu/m generation has offered many new challenges for semiconductor manufacturing. Two are discussed in this paper. The firstExpand
  • 7
Polynomial Chebyshev Approximations of the Ideal Filter
Chebyshev error norms of polynomial approximations of the ideal filter complex transmittance are defined and procedures are developed to minimize these norms. The method emphasizes the role of theExpand
  • 5