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Formal Methods for Scheduling of Latency-Insensitive Designs
This work provides a formal modeling of RS and SW, that can be then formally verified, and turns out, resulting behavior is k-periodic, thus amenable to static scheduling.
State-based representation of CCSL operators
The Clock Constraint Specification Language (CCSL) was devised to offer a formal support to conduct causal and temporal analyses on MARTE models and this work introduces formally a state-based semantics for CCSL operators.
Compositional Verification of Software Product Lines
This paper presents a novel approach to the design verification of Software Product Lines (SPL), which ensures that every product at the design level behaviourally conforms to a products at the requirement level.
Tracing SPLs precisely and efficiently
- S. Mohalik, S. Ramesh, J. Millo, S. Krishna, Ganesh Khandu Narwane
- Computer ScienceSPLC '12
- 2 September 2012
A precise and formal definition of implementability over a fairly expressive traceability relation is given to solve a set of useful analysis problems that are either refinements of known problems, or are completely novel.
Periodic scheduling of marked graphs using balanced binary words
Traceability Analyses between Features and Assets in Software Product Lines
- Ganesh Khandu Narwane, J. Galindo, S. Krishna, David Benavides, J. Millo, S. Ramesh
- Computer ScienceEntropy
- 3 August 2016
A precise and formal definition of implementability over a fairly expressive traceability relation is introduced and a new approach to solve analysis problems by encoding them as Quantified Boolean Formulae (QBF) and solving them through Quantified Satisfiability (QSAT) solvers.
Ordonnancements périodiques dans les réseaux de processus : Application à la conception insensible aux latences. (Static scheduling in process networks : application to latency insentitive design)
- J. Millo
- Computer Science, Philosophy
- 15 December 2008
Du fait de la miniaturisation grandissante des circuits electroniques, la conception de systeme sur puce actuelle, se heurte au probleme des latences sur les fils d'interconnexions traversant tout le…
Relating Requirement and Design Variabilities
- J. Millo, S. Ramesh
- Computer Science19th Asia-Pacific Software Engineering Conference
- 4 December 2012
This paper presents a novel approach to relate the variabilities that exist at the requirement and design levels in a Software Product Line (SPL) based upon the well-known automata containment algorithm used in formal verification of finite state systems.
Safe CCSL specifications and marked graphs
- F. Mallet, J. Millo, R. Simone
- Computer ScienceEleventh ACM/IEEE International Conference on…
- 21 November 2013
A sufficient condition to detect that the product is actually safe is proposed, done by abstracting each CCSL constraint (relation and expression) as a marked graph, and detecting that some specific places, called counters, in the resulting marked graph are safe is sufficient to guarantee that the composition is safe.
Boundness Issues in CCSL Specifications
The Clock Constraint Specification Language (CCSL), first introduced as a companion language for MARTE, was devised to offer a formal support to conduct causal and temporal analyses on MARTe models.