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A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films
This paper presents a new two-dimensional (2-D) low pass filter model for the prediction of post-chemical-mechanical polishing (CMP) die level wafer topography variation caused by the interconnect
Interface Characterization of HfO2/GaSb MOS Capacitors With Ultrathin Equivalent Oxide Thickness by Using Hydrogen Plasma Treatment
We investigate p-type GaSb MOS capacitors with various HfO2 thicknesses grown using an atomic layer deposition. GaSb surfaces treated with ex-situ chemical solution and in situ remote hydrogen plasma
Characterization of polysilicon-encapsulated local oxidation
Device isolation has been most commonly achieved through the use of local oxidation of silicon (LOCOS) or LOCOS derivatives. LOCOS is a highly dependable, low-defect isolation technique, which
The effect of biased spacers on LDD MOSFET behavior
The concept of using LDD spacers that are independently biased with respect to the gate electrode is presented. It is shown that the lateral electric field is strongly influenced by the drain
Scaling of poly-encapsulated LOCOS for 0.35 /spl mu/m CMOS technology
We demonstrate the scaling of Poly-Encapsulated LOCOS (PELOX) for 0.35 /spl mu/m CMOS technology without detrimental effects on gate oxide and shallow source/drain junction integrity. As-grown bird's
A high-performance quadruple well, quadruple poly BiCMOS process for fast 16 Mb SRAMs
An advanced, high-performance BiCMOS technology has been developed for fast 16Mb SRAMs. A split word-line bitcell architecture, using four levels of polysilicon and two self-aligned contacts,
Recessed polysilicon encapsulated local oxidation
Local oxidation of silicon (LOCOS) is the most commonly used isolation technology in silicon integrated circuits. The inherently large field oxide encroachment associated with LOCOS severely limits