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On-chip high-voltage generation in MNOS integrated circuits using an improved voltage multiplier technique
TLDR
An improved voltage multiplier technique has been developed for generating +40 V internally in p-channel MNOS integrated circuits to enable them to be operated from standard +5- and -12-V supply rails. Expand
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On-Chip High-Voltage Generation in Integrated Circuits Using an Improved Multiplier Technique
TLDR
An improved oped for generating +40 voltage multiplier technique has been develV internally in p-channel MNOS integrated circuits to enrtble them to be operated from standard +5and : 12-V supply rails. Expand
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  • 27
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Design trade-offs and reliability of power circuit substrates with respect to varying geometrical parameters of direct copper bonded Al/sub 2/O/sub 3/ and BeO
This paper describes preliminary work performed to develop adhesion as well as thermal cycle reliability data for the DBC-Al/sub 2/O/sub 3/ and DBC-BeO substrates. Samples of direct copper bondedExpand
  • 3
New charge-differencing technique for c.c.d. transversal filters
A new charge-differencing technique for use with c.c.d. transversal filters employing charge sensing is described. The method eliminates the need for a voltage-differencing amplifier and requires theExpand
  • 1
Adaptive cancellation of fixed-pattern noise in c.c.d. serial-parallel-serial memory
TLDR
The letter addresses the problem of the effective implementation of long analogue delay lines. Expand
  • 1
M.N.O.S. Non-Volatile Quad Latch
  • J. F. Dickson, D. Bostock
  • Medicine, Computer Science
  • First European Solid State Circuits Conference…
  • 1 September 1975
TLDR
The basic element of the technology is the M.E.N.S. memory transistor. Expand