Skip to search formSkip to main contentSkip to account menu
Static scheduling of a Time-Triggered Network-on-Chip based on SMT solving
TLDR
This paper tackles the TTNoC scheduling problem and presents an approach based on Satisfiability Modulo Theories (SMT) solving that integrates SMT solving into classical heuristic algorithms.
View on ACM
Software Defined Networking for Communication and Control of Cyber-Physical Systems
TLDR
The proposed SDN architecture for industrial automation aims to leverage Industry 4.0 and Smart Factories, to bring together industrial automation installations with networking and Internet technologies.
View on IEEE
Software Defined Networks in Industrial Automation
TLDR
This paper proposes a network architecture called the Software Defined Industrial Automation Network (SDIAN), with the objective of improving network scalability and efficiency, and analytically quantify the proposed solutions that alleviate the overhead incurred from the flow setup.
View PDF
A Formal Correctness Proof for Code Generation from SSA Form in Isabelle/HOL
TLDR
A formal semantics for static single assignment (SSA) intermediate representations is developed and it is proved formally within the Isabelle/HOL theorem prover that a relatively simple form of code generation preserves the semantics of the transformed programs in SSA form.
View Paper
Analysis and optimization of fault-tolerant task scheduling on multiprocessor embedded systems
TLDR
This is the first approach in fault-tolerant task scheduling that considers permanent and transient faults in a unified manner and the effectiveness of this approach is illustrated using several case studies.
View on ACM
Towards Formal Monitoring of Workpieces in Agile Manufacturing
TLDR
A state-machine-based approach for monitoring workpieces using sensors such as RFID readers and OPC UA where each object is represented as a deterministic state machine to monitor the object's journey throughout production via this state machine representation.
View on IEEE
Verification of PLC Properties Based on Formal Semantics in Coq
TLDR
The proposed formal semantics of two languages defined in the IEC 61131-3 standard for PLC programming, a graphical high-level language that allows to describe the main control-flow of the system, and an associated tool for automatically generating SFC representations from a graphical description.
View via Publisher
Optimizing Code Generation from SSA Form: A Comparison Between Two Formal Correctness Proofs in Isabelle/HOL
View via Publisher
Formal Verification of Java Code Generation from UML Models
TLDR
This paper presents the approach to formally verify within the Isabelle/HOL theorem prover that a certain algorithm for Java code generation from UML specifications is semantically correct.
Formal verification of dead code elimination in Isabelle/HOL
TLDR
This paper formally verify dead code elimination (DCE) within the theorem prover Isabelle/HOL, and reformulate the algorithm so that it is applicable to static single assignment (SSA) form which is a state of the art intermediate representation in modern compilers, thereby showing that DCE is significantly simpler on SSA form than on classical intermediate representations.
View on IEEE
...
...
By clicking accept or continuing to use the site, you agree to the terms outlined in our Privacy Policy, Terms of Service, and Dataset License