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Robust SEU Mitigation of 32 nm Dual Redundant Flip-Flops Through Interleaving and Sensitive Node-Pair Spacing
We introduce the 32 nm SOI Boeing Interleaved Flip-Flop, which is based on the DICE topology with additional RHBD layout enhancements. Sensitive node pairs were separated by interleaving elements ofExpand
Predicting the Single-Event Error Rate of a Radiation Hardened by Design Microprocessor
We describe the approach used to calculate and verify on-orbit upset rates of radiation hardened microprocessors. System designers use these error rates to choose between microprocessors and addExpand
Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor
A complex processor was synthesized using an RHBD cell library and fabricated in a commercial 90 nm CMOS technology. Single Event Effects testing revealed transients on the clock and global resetExpand
A method for efficient Radiation Hardening of multicore processors
This paper describes a method for developing Radiation Hardened by Design (RHBD) multicore processor Integrated Circuits (ICs) that meet specific single-event error rate targets in space environmentsExpand
High density DRAM for space utilizing embedded DRAMs macros in 32nm SOI CMOS
• Ultra deep submicron SOI CMOS with eDRAM enables space hardened high density memories • Significant benefit for high performance data processors • Techniques exist to mitigate SEE challenges inExpand
Estimating SEE Error Rates for Complex SoCs With ASERT
This paper describes the ASIC Single Event Effects (SEE) Error Rate Tool (ASERT) methodology to estimate the error rates of complex System-on-Chip (SoC) devices. ASERT consists of a top-down analysisExpand