• Publications
  • Influence
VTR 7.0: Next Generation Architecture and CAD System for FPGAs
TLDR
VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. Expand
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LegUp: high-level synthesis for FPGA-based processor/accelerator systems
TLDR
In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand
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The VTR project: architecture and CAD for FPGAs from verilog to routing
TLDR
This paper describes the current status and new release of an ongoing effort to create such a flow - the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. Expand
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LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
TLDR
We introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand
  • 260
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A Survey and Evaluation of FPGA High-Level Synthesis Tools
  • R. Nane, V. Sima, +9 authors K. Bertels
  • Engineering, Computer Science
  • IEEE Transactions on Computer-Aided Design of…
  • 1 October 2016
TLDR
High-level synthesis (HLS) is increasingly popular for the design of high performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. Expand
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A PUF design for secure FPGA-based embedded systems
  • J. Anderson
  • Engineering, Computer Science
  • 15th Asia and South Pacific Design Automation…
  • 18 January 2010
TLDR
The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counter-piracy. Expand
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Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
TLDR
The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. Expand
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Source-level debugging for FPGA high-level synthesis
TLDR
We describe a source-level debugging framework for FPGA high-level synthesis (HLS) that offers gdb-like step, break, and data inspection functionality for an HLS-generated hardware circuit. Expand
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Analytical placement for heterogeneous FPGAs
TLDR
We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based logic blocks, multiplier/DSP blocks and block RAMs that delivers a 4× speedup, on average, compared to Altera's non-timing driven flow, at the cost of a 9% reduction in maximum operating frequency. Expand
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Active leakage power optimization for FPGAs
  • J. Anderson, F. Najm
  • Engineering, Computer Science
  • IEEE Trans. Comput. Aided Des. Integr. Circuits…
  • 1 November 2006
TLDR
Two "no cost" approaches for active leakage reduction are presented for field-programmable gate arrays (FPGAs). Expand
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