J. Anderson

Publications
Influence

VTR 7.0: Next Generation Architecture and CAD System for FPGAs

Jason Luu, Jeffrey B. Goeders, +11 authors Vaughn Betz
Computer Science
TRETS
1 June 2014

VTR can now generate a netlist of the final post-routed circuit which enables detailed simulation of a design for a variety of purposes. Expand

LegUp: high-level synthesis for FPGA-based processor/accelerator systems

Andrew Canis, Jongsok Choi, +5 authors T. Czajkowski
Computer Science
FPGA '11
27 February 2011

In this paper, we introduce a new open source high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand

The VTR project: architecture and CAD for FPGAs from verilog to routing

Jonathan Rose, Jason Luu, +6 authors J. Anderson
Computer Science
FPGA '12
22 February 2012

This paper describes the current status and new release of an ongoing effort to create such a flow - the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. Expand

LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems

Andrew Canis, Jongsok Choi, +5 authors J. Anderson
Computer Science
TECS
1 September 2013

We introduce a new high-level synthesis tool called LegUp that allows software techniques to be used for hardware design. Expand

A Survey and Evaluation of FPGA High-Level Synthesis Tools

R. Nane, V. Sima, +9 authors K. Bertels
Engineering, Computer Science
IEEE Transactions on Computer-Aided Design of…
1 October 2016

High-level synthesis (HLS) is increasingly popular for the design of high performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today's system complexity. Expand

A PUF design for secure FPGA-based embedded systems

J. Anderson
Engineering, Computer Science
15th Asia and South Pacific Design Automation…
18 January 2010

The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counter-piracy. Expand

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

Jason Luu, J. Anderson, Jonathan Rose
Computer Science
FPGA '11
27 February 2011

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. Expand

Source-level debugging for FPGA high-level synthesis

Nazanin Calagar, S. Brown, J. Anderson
Computer Science
24th International Conference on Field…
20 October 2014

We describe a source-level debugging framework for FPGA high-level synthesis (HLS) that offers gdb-like step, break, and data inspection functionality for an HLS-generated hardware circuit. Expand

Analytical placement for heterogeneous FPGAs

Marcel Gort, J. Anderson
Computer Science
22nd International Conference on Field…
25 October 2012

We present HeAP, an analytical placement algorithm for heterogeneous FPGAs comprised of LUT-based logic blocks, multiplier/DSP blocks and block RAMs that delivers a 4× speedup, on average, compared to Altera's non-timing driven flow, at the cost of a 9% reduction in maximum operating frequency. Expand

Active leakage power optimization for FPGAs

J. Anderson, F. Najm
Engineering, Computer Science
IEEE Trans. Comput. Aided Des. Integr. Circuits…
1 November 2006

Two "no cost" approaches for active leakage reduction are presented for field-programmable gate arrays (FPGAs). Expand

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