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FPGA Implementation of Blowfish Cryptosystem Using VHDL
A Novel Approach of Modified Run Length Encoding Scheme for High Speed Data Communication Application
This paper presents a Modified Run Length Encoding (RLE) Scheme for High Speed Data Compression. Compression is efficient technique to reduce the memory occupancy and to improve the performance ofExpand
Modeling A New Architecture Of Area Delay Efficient 2-D Fir Filter Using VHDL
TLDR
T his paper presented memory footprint and combinational complexity for two - dimensional finite impulse response (FIR) filter to get the systematic design strategy to obtain area-delay-power-efficient architectures. Expand
Design of High Speed Area & Power Efficient Parallel Prefix Adders with QCA Majority Logic
As transistors reduce in size more and more of them can be accommodated in a one die, thus growing chip computational capabilities. However, transistors cannot find much lesser than their currentExpand
Design for Exterminating Synchronization Latency Using Sequenced Latching
TLDR
We propose a method that performs speculative computations during synchronization cycles and hence prevented synchronization time from incurring abeyance by overlapping it with computation cycles. Expand
Design of Efficient FIR filter with EDBNS multiplier using Transpose method for various Applications
In FIR Filter Realization, Transpose form FIR filters are naturally pipelined and support multiple constant multiplication (MCM) technique that results in major saving of computation. By includingExpand
Implementation Of Fully-Pipelined 16-Point DHT Architectures Using 8-Point And 4-Point DHTs for FPGA Realization
TLDR
Fully-pipelined simple modular structures are presented in this project for efficient hardware realization of Discrete Hadamard transform. Expand
FPGA Realization of Secured Hash Algorithm with Parallel Architecture
TLDR
Secure Hash Algorithm is the most widely used Hash function in the world which is mainly used for security based applications. Expand
FPGA Implementation of New Architecture
TLDR
The paper mainly focus on a development of a new architecture of a BCD parallel multiplier that utilizes some properties of two different redundant BCD codes to speed up its computation. Expand
A New Novel Low Power Floating Point Multiplier Implementation Using Vedic Multiplication Techniques
In this paper, Vedic Multiplication Technique is used to implement IEEE 754 Floating point multiplier. The Urdhva-triyak bhyam sutra is used for the multiplication of Mantissa. The underflow and overExpand
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