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A 45nm Logic Technology with High-k+Metal Gate Transistors, Strained Silicon, 9 Cu Interconnect Layers, 193nm Dry Patterning, and 100% Pb-free Packaging

• K. Mistry, C. Allen, +51 authors Karl A. Zawadzki
• 2007 IEEE International Electron Devices Meeting
• 2007

A 45 nm logic technology is described that for the first time incorporates high-k + metal gate transistors in a high volume manufacturing process. The transistors feature 1.0 nm EOT high-k gate… (More)

Measurements and analysis of SER-tolerant latch in a 90-nm dual-V/sub T/ CMOS process

• Peter Hazucha, Tanvi Karnik, +8 authors S. Borkar
• IEEE Journal of Solid-State Circuits
• 2004

We designed a soft error rate (SER) tolerant latch utilizing local redundancy. We implemented a test chip containing both the standard and SER-tolerant latches in a 90-nm dual-V/sub T/ CMOS process.… (More)

Radiation-Induced Soft Error Rates of Advanced CMOS Bulk Devices

• Nathalie Seifert, P. Slankard, +7 authors J. A. Maiz
• 2006 IEEE International Reliability Physics…
• 2006

This work provides a comprehensive summary of radiation-induced soft error rate (SER) scaling trends of key CMOS bulk devices. Specifically we analyzed the SER per bit scaling trends of SRAMs,… (More)

Impact of CMOS process scaling and SOI on the soft error rates of logic processes

• Scott Hareland, J. A. Maiz, M. Alavi, K. Mistry, S. Walsta, Changhong Dai
• 2001 Symposium on VLSI Technology. Digest of…
• 2001

Technology scaling, reduction in operating voltages, and the increase in cache size and circuit complexity have been key enablers to achieving the performance improvement expectation dictated by… (More)

Characterization of multi-bit soft error events in advanced SRAMs

• J. A. Maiz, Scott Hareland, K. Zhang, P Armstrong
• IEEE International Electron Devices Meeting 2003
• 2003

Error correction code schemes are being implemented in memories and microprocessor caches in response to SER increases which result from increasing bit counts and technology scaling. These methods… (More)

BTI reliability of 45 nm high-K + metal-gate process technology

• S. Pae, M. Agostinelli, +19 authors Jami Wiedemer
• 2008 IEEE International Reliability Physics…
• 2008

In this paper, bias-temperature instability (BTI) characterization on 45nm high-K + metal-gate (HK+MG) transistors is presented and degradation mechanism is discussed. Transistors with an unoptimized… (More)

Neutron soft error rate measurements in a 90-nm CMOS process and scaling trends in SRAM from 0.25-/spl mu/m to 90-nm generation

• Peter Hazucha, Tanvi Karnik, +7 authors S. Borkar
• IEEE International Electron Devices Meeting 2003
• 2003

The neutron soft error rate (SER) dependency on voltage and area was measured for a state-of-the-art 90-nm CMOS technology. The SER increased by 18% for a 10% reduction in voltage, and scaled… (More)

Effect of BTI Degradation on Transistor Variability in Advanced Semiconductor Technologies

• Sangwoo Pae, J. A. Maiz, Chandra Prakash Prasad, Bruce Woolery
• IEEE Transactions on Device and Materials…
• 2008

The effect of PMOS transistor negative bias temperature instability (NBTI) on product performance is a key reliability concern. As technology scales and device dimensions shrink, the trend in the… (More)

Dielectric breakdown in a 45 nm high-k/metal gate process technology

• Chandra Prakash Prasad, M. Agostinelli, +23 authors Jami Wiedemer
• 2008 IEEE International Reliability Physics…
• 2008

In this paper, we present extensive breakdown results on our 45nm HK+MG technology. Polarity dependent breakdown and SILC degradation mechanisms have been identified and are attributed gate and… (More)

A high performance 180 nm generation logic technology

• S. Yang, S. Ahmed, +22 authors Marietta Boje Bohr
• International Electron Devices Meeting 1998…
• 1998

A 180 nm generation logic technology has been developed with high performance 140 nm L/sub GATE/ transistors, six layers of aluminum interconnects and low-/spl epsi/ SiOF dielectrics. The transistors… (More)

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