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A soft-core processor is a hardware description language (HDL) model of a specific processor (CPU) that can be customized for a given application and synthesized for an ASIC or FPGA target. In many applications, soft-core processors provide several advantages over custom designed processors such as reduced cost, flexibility, platform independence and(More)
The status of codebook based MU MIMO feedback schemes in different wireless standards are briefly overviewed. Based on the Normal Feedback Scheme to feedback the preferred Precoding Matrix Index (PMI), a Best Companion Pairing (BCP) scheme and a Best Companion Cluster (BCC) scheme are introduced to make more efficient pairing. Besides the preferred PMI, UE(More)
Profiling is the analysis of a software program's behaviour as it is executing on a target processor or platform. The purpose is to determine the computational bottleneck so that designers can modify or optimize the software code in order to gain a speed up in overall performance. There is a variety of profiling tools available which provides different(More)
The reconfigurable array with slotted optical buses (RASOB) has recently received a lot of attention from the research community. In this paper, we first discuss the reconfiguration methods and communication capabilities of the RASOB architecture. Then, we use this architecture for the implementation of efficient sorting algorithms on the 1D RASOB and the(More)
This paper studies the impact of chaining and several instruction scheduling schemes on one-memory-port vector supercomputers, illustrated by the Cray-1 and Cray-2. The lack of instruction chaining in the Cray-2 vector processor requires a different instruction scheduling scheme from that of the Cray-1. Situations are characterized in which <italic>simple(More)
This paper presents an analysis and comparison of the profiled results using software-based profilers (SBP) and FPGA-based profilers (FPGA-BP) for a Nios II Processor system. SBP tools are commonly used to detect performance bottlenecks of a program by applying instrumentation code at the binary level and using sampling methods for performance data(More)
To stay competitive at the start of the 21st century, manufacturing companies are in great need of support for designing/redesigning their production systems in accordance with the drastically, rapidly and frequently changing environment. Our aim is to develop a computer-guided system for the design of factories in the manufacturing industry. As a first(More)
This work presents a hardware-efficient and low-overhead scheme for mitigating the phase noise (PN) and full-range carrier frequency offset (CFO) in multi-input multi-output orthogonal frequency division multiplexing systems. To estimate the phase error due to PN and CFO, radio frequency pilot is used and only one pilot subcarrier is required per antenna.(More)