J. S. Kang

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In this work, a new efficient simulation method with comprehensive physical models is developed to evaluate the performance of CTM at various biases, temperatures, and gate stack configurations. The dominant physical mechanisms on the P/E/R operations of CTM are clarified.
An improved program mode for memory array based on ferroelectric field effect transistor (Fe-FET) is proposed. A SPICE macro-model for the transfer characteristics of Fe-FET devices, based on the Schmitt trigger circuit, is demonstrated and applied to circuit simulation. The simulation results show that, compared to the conventional program mode, the(More)
High quality thermal robust CVD-HfO/sub 2/ gate dielectrics with HfN electrodes were fabricated. The scalability of the HfN/HfO/sub 2/ gate stack and the integration issues with CMOS devices were systematically investigated. The equivalent oxide thickness (EOT) is aggressively scaled down to 0.65 nm with low gate leakage and excellent reliability(More)
The extended flicker noise measurement incorporating with BTI evaluation is applied to investigate the bulk trapping density N<inf>t</inf> in HK/MG stacks and the correlated BTI behaviors. An effective evaluating technique on BTI/TDDB is developed. This method will help to understand the physical original of BTI degradation.
The velocity overshoot effect has been simulated in nano-scale double gate MOSFETs and compared by different simulation method including hydrodynamic model (HD model) and Monte Carlo method (MC method). As we know, the hydrodynamic model tends to overestimate the velocity overshoot, so how much the overestimate of HD model can reach to, and how this(More)
Gd doped TiO<sub>2</sub> poly crystalline thin film was prepared on Pt/Ti/SiO<sub>2</sub>/Si substrates by sol-gel method. Nonvolatile and reversible bistable resistance states were demonstrated for the first time. Excellent reversible resistive switching characteristics with 0.6 plusmn 0.1V reset bias and 2.0 plusmn 0.1V set bias and a resistance(More)
The mobility degradation in ultrathin-body (UTB) SOI MOSFETs with high-k gate stack induced by Coulomb scattering rates is studied. The Coulomb scattering limited electron mobility for different gate dielectric materials and different silicon body thickness are calculated based on Coulomb scattering theories. The results show that increasing the dielectric(More)
Based on our recent investigation on HfO/sub 2/ high-k gate dielectrics, we review the Hf based gate dielectric in the future ULSI CMOS devices in the following aspects: How long HfO/sub 2/ can be used satisfactorily, assessed from the gate tunneling and scalability; how thin EOT can be grown technologically assessed by interfacial layer thickness; and how(More)
The characteristics of both n- and p- GOI MOSFETs are simulated by 2D self-consistent full-band MC method based on quantum Boltzmann equation to evaluate the scaling behaviors between GOI and SOI MOSFETs. The simulation results indicate that both for n and p channel GOI MOSFETs have favorable scaling properties in nano-scale due to the non-stationary(More)
Tension-free inguinal mesh-plug hernioplasty is well established. However, femoral hernia repair remains challenging and controversial. We aimed to evaluate a preperitoneal approach of tension-free hernioplasty for femoral hernia upon the anatomy rationality. A prospective study of 62 patients between October 1999 and June 2011 received femoral hernioplasty(More)