J. S. Davis

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A multipurpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods operating up to 4.4Gpbs. The digital test core(More)
This paper presents a strategy for testing future generations of wafer-level packaged logic devices that have nanoscale I/O structures. The strategy assumes that the devices incorporate built-in self test (BIST) features so that only a subset of the functional I/O needs to be directly accessed during testing. A miniature tester is described that provides(More)
A multipurpose digital test core utilizing programmable logic has been introduced [1,2] to implement many of the functions of traditional automated test equipment (ATE). While previous papers have described the theory, this paper quantifies the results and presents additional applications with improved methods. The digital test core provides a substantial(More)
A programmable FPGA-based digital logic circuit is enhanced with high-speed emitter-couple logic and optoelectronics laser drivers and receivers to create a testbed for evaluating methods of transferring parallel data words in sub-nanosecond bursts. The end application requires the transfer of entire address/data buss information within a single cycle of(More)
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