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We discuss in this paper the influence of the presence of an elevated strike object on the peak of the lightning return stroke current determined from remote field measurements. We develop analytical expressions relating the lightning return stroke channel-base current and the far electromagnetic field for different specific cases, namely, (1)(More)
Two 128-point 16-bit radix-2 FFT/IFFT processors based on synchronous-logic (sync) and asynchronous-logic (async) for low voltage (1.1-1.4 V) energy-critical low-speed hearing aids are described. The two processors herein are designed with the same function and similar architecture, and the emphasis is energy efficacy. The async approach, on average,(More)
This paper presents an analysis of lightning return strokes to tall structures. The interaction of lightning with a tall structure is modeled using the antenna theory. The finite ground conductivity as well as the buried grounding system of the tall structure are taken into account in the analysis. It is shown that the current waveform, in sections of the(More)
An inductorless low-noise amplifier (LNA) design for ultra-wideband (UWB) receiver front-end is presented. Without on-chip inductors, the ultra-wide bandwidth is achieved by a syncretic adoption of thermal noise canceling, capacitor peaking, and current reuse. Fabricated in a 0.13-mum CMOS technology, the LNA exhibits a small signal gain of 11-dB and a -3-d(More)
The design of a low-voltage micropower asynchronous (async) signed truncated multiplier based on a shift-add structure for power-critical applications such as the low-clock-rate (<4 MHz) hearing aids is described. The emphases of the design are micropower operation and small IC area, and these attributes are achieved in several ways. First, a maximum of(More)
One of the main components in a digital class D amplifier is the digital modulator. This modulator is necessary so that an N-bit digital input can be converted into 1-bit modulated pulses, which in turn are used for high efficiency operation in the output stage of the class D amplifier. In this paper, we review three design methods for digital modulators.(More)
The carry-completion sensing adders (CCSAs) are widely adopted for fast average-case low energy asynchronous (async) adders. Despite its carry-completion sensing property, completion detection in the conventional CCSAs suffers from potential timing violations (PTVs); conventional CCSAs would otherwise require additional hardware or detailed design(More)
In this paper, we investigate the energy efficacy of the asynchronous (async) logic over its synchronous (sync) counterpart in a 128-point FFT/IFFT processor for low voltage (1.1V to 1.4V) energy-critical medium-to-low speed applications including hearing aids. Both async and sync designs are implemented using the same process (0.35μm CMOS) and having(More)
Self-Adaptive V<sub>DD</sub> Scaling (SAVS) technique achieves power/energy reduction by dynamically scaling V<sub>DD</sub> for the prevailing conditions. However, when applied in sub-threshold (sub-V<sub>t</sub>) region, robustness issues need to be addressed due to the severe delay uncertainty associated with sub-V<sub>t</sub> Process, Voltage, and(More)
An ultra-low power sub-threshold Finite Impulse Response (FIR) filter bank for hearing aid applications is demonstrated in 65nm CMOS technology. The system has a 2kb Static Random Access Memory (SRAM) interface optimized for sub-threshold operation. The system operates at 0.3V sub-threshold regime and consumes 10.4 &#x03BC;W at 0.96MHz clock frequency which(More)