Learn More
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of the CMOS technology, thanks to their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic(More)
Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic(More)
RF losses and non-linear behavior of RF passive elements such as coplanar transmission lines and inductors are analyzed. The investigated trap-rich HR-Si wafers with a fixed oxide layer of 150 nm-thick show true effective resistivity values higher than 4 kΩ-cm up to 5 GHz and harmonic distortion levels lower than -90 dBm for a 900 MHz input with(More)
Non-linear behaviour of RF coplanar transmission lines is analyzed for various values of Si substrate resistivitiy. Based on small-signal measurements performed under different DC bias conditions, voltage dependent capacitance and conductance per unit length of the transmission line are extracted and compared for several silicon substrates. Harmonic(More)
In this paper, a semi-analytical extrinsic gate capacitance model for Triple Gate FinFET, based on three-dimensional numerical simulations, is presented. The model takes into account the source/drain electrode and contact areas. It includes 5 capacitance components that describe the different fringing electrical couplings that exist inside the FinFET(More)
We present for the first time the RF and linear performance of commercial 200 mm trap-rich HR-SOI wafers. These wafers are fully compatible with the thermal budget of CMOS process. The investigated SOI wafers with a fixed BOX of 400 nm-thick show effective resistivity values higher than 4 kΩ-cm and harmonic distortion levels lower than -81 dBm for a(More)
This paper analyzes RF losses and non-linear behavior from room temperature up to 175&#x00B0;C of coplanar waveguide (CPW) and thin film microstrip (TFMS) lines fabricated on both High Resistivity (HR) and Standard resistivity (STD) Silicon-on-Insulator (SOI) substrates. Through measurements it is shown that CPW topology exhibits larger 2<sup>nd</sup>(More)
A methodology to properly establish an accurate SOI FinFET compact model through SPICE simulator is presented. This compact model is implemented in Verilog-A to simulate the performance of RF circuits based on SOI FinFET technology. It predicts well static behavior of the transistor and circuit, as well as their small-signal RF behavior by modeling the(More)
RF performance of ultra-thin body with ultra-thin buried oxide (BOX), so-called UTBB, MOSFETs with gate length down to 30 nm is presented. Current gain cut-off frequency f<sub>T</sub> and maximum oscillation frequency f<sub>max</sub> of 160 GHz and 143 GHz, respectively, are demonstrated. Based on an accurate extraction of the small-signal equivalent(More)
  • 1