J. P. Colinge

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This paper demonstrates that fully-depleted (FD) silicon-on-insulator (SOI) technology offers unique opportunities in the ®eld of low-voltage, low-power CMOS circuits. Beside the well-known reduction of parasitic capacitances due to dielectric isolation, FD SOI MOSFETs indeed exhibit near-ideal body factor, subthreshold slope and current drive. These assets(More)
We present a new fully self-aligned single-electron memory with a single pair of nano floating gates, made of different materials (Si and Ge). The energy barrier that prevents stored charge leakage is induced not only by quantum effects but also by the conduction-band offset that arises between Ge and Si. The dimensions and position of each floating gate(More)
In this paper we will do the analysis of the gate engineering impact on tri state inverter performance for the application on SOC that is system on chip with the help of different high dielectric material. The high dielectric materials used in electronic circuits for preventing tunnelling effect which will increase the thermally generated current. In order(More)
As the channel lengths of conventional planar metal oxide semiconductor field effect transistor (MOSFET) shrink into the nano meter regime, performance of the devices becomes degraded mainly because of short channel effects. The nano range silicon on insulator metal oxide semiconductor field effect transistors (SOI-MOSFET) with Multi gate around the silicon(More)
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