J. P. Anita

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With the advent of VLSI, very complex circuits can be implemented in a single chip. So the need for testing the chip increases with the integration. Fault diagnosis results in improving the circuit design process, the manufacturing yield, cost of testing and also reduces the time to market. Diagnosis of today's complex faults is a challenging problem due to(More)
A technique is proposed for diagnosing multiple faults in a given erroneous circuit with improved diagnosis resolution The first technique is based on Single Location At a Time (SLAT) and path tracing techniques which starts with an imrial fault list obtained from an existing diagnosis method. The single observation — single location at a time(More)
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