J. Mitani

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— An SoC with ARM® Cortex™-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted Channel™ (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via V DD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at(More)
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